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Standard ICs
Picture cell driver for STN (LCD driver) for low voltage power supplies
BU9718KV
The BU9718KV is a driver IC designed for the character-type STN liquid crystal panels which are ideal for applications such as portable devices. The number of display segments includes 32 output segments and 3 common outputs, enabling drive of up to 96 segments. A compact 48-pin QFP package with a pitch of 0.5 mm is used, enabling compact size for the set as a whole.
*Applications (POS, ECR, PDA, and others), Portable terminals
movie projectors, cameras, telephones (cordless hand-
held telephone units), and others Low-voltage power supply sets 4) Up to 32 segment output pins and 3 common output pins are provided, enabling a total display of up to 96 segments. 5) 1 / 3 duty display. 6) Either 1 / 2 or 1 / 3 bias can be selected for power supply for LCD display.
Limits - 0.3 ~ + 7.0 - 0.3 ~ VDD + 0.3 - 0.3 ~ VDD + 0.3 300 3 400 2 - 55 ~ + 125 Unit V V V A mA mW C
*Features on 3V power supply. 1) Operates
2) Low current dissipation. (0.1A in low power mode (actual value)) 3) Compact package. (molded section is 7.0 mm )
*Absolute maximum ratings (Ta = 25C, VSS = 0V)
Parameter Power supply voltage1 Input voltage1 Output voltage1 Output current Power dissipation Storage temperature Symbol VDD VIN VOUT ISO ICO Pd Tstg Pin VDD OSC, CS, CK, DI, RES OSC S1 ~ S32 COM1 ~ COM3 -- --
1 Max. voltage that can be applied with a VSS pin 2 Reduced by 4.0mW for each increase in Ta 1C over 25C.
*Recommended operating conditions (Ta = 25C, VSS = 0V)
Parameter Power supply voltage Input voltage Oscillation freq., with external input External resistance External capacitance Operating temperature Symbol VDD VDD1 VDD2 fOSC R C Topr Pin VDD VDD1 VDD2 OSC OSC OSC -- Min. 2.7 0 0 -- -- -- - 40 Typ. -- 2 / 3 VDD 1 / 3 VDD 38 47 1000 -- Max. 3.5 VDD VDD 100 -- -- 85 Unit V V V kHz k pF C
Indicates the max. voltage that can be applied with a VSS pin. 1
Standard ICs
BU9718KV
*Block diagram
VDD1 VDD2 LCD Power
RES CS DI CK CTRL Logic Data Latch
OSC
OSC
Common Driver
Segment Driver
S30
S31
COM1
COM2
COM3
COM1
*Pin assignments
37
36
COM2 COM3 RES VDD VDD1 VDD2 VSS OSC CS CK DI N.C.
25 24
N.C. S22 S21 S20 S19 S18
VQFP48
N.C.
S32
S31
S30
S29
S28
S27
S26
S25
S24
S23
S17 S16 S15 S14 S13
48 1
S10 S11 S1 S2 S3 S4 S5 S6 S7 S8 S9
13 12
N.C.
S12
2
S32
S1
S2
S3
S4
Standard ICs
BU9718KV
*Pin descriptions
Pin No. 1--11 13--23 26--35 36 37 38 39 44 45 46 47 41 42 Pin name S1--S11 S12--S22 S23--S32 COM1 COM2 COM3 RES OSC CS CK DI VDD1 VDD2 I/O O Function Segment data output pin; outputs LCD drive voltage that matches COM1 - COM3 compatible data Common drive output; frame freq. fC = (fOSC / 384) Hz Reset input; when RES = L, resets internal data (include. control data) Oscillation pin (for common, segment alternation waves) Chip segment input; when CS = H, data can be transferred Synchronous clock input for serial data transfer Serial data input Internal standard voltage for liquid-crystal drive; when using 1 / 2 bias mode, connects to VDD2 Internal standard voltage for liquid-crystal drive; when using 1 / 2 bias mode, connects to VDD1 Processing when not in use OPEN
O
VSS
I -- I I I -- --
VDD VSS VSS VSS VSS OPEN OPEN
* Electrical characteristics (unless otherwise noted, Ta = 25C, VDD = 2.7V to 3.5V, VSS = 0V)
Parameter Input high level voltage Input low level voltage Input high level current Input low level current Output high level voltage Symbol VIH VIL IIH IIL VSOH VCOH VSOL VCOL VCM1 VSM1 Output medium level voltage VCM2 VSM2 VCM3 Power supply current IQ IDD Min. 0.8 VDD 0 0 0 -- -- -- -- -- -- -- -- -- -- -- Typ. -- -- -- -- VDD - 1.0 VDD - 1.0 1.0 1.0 1 / 2 VDD 1.0 2 / 3 VDD 1.0 2 / 3 VDD 1.0 1 / 3 VDD 1.0 1 / 3 VDD 1.0 0.1 100 Max. VDD 0.2 VDD 6.0 6.0 -- -- -- -- -- -- -- -- -- 30 300 Unit V V A A V V V V V V V V V A A Conditions -- -- VI = VDD VI = VSS IO = - 20A IO = - 100A IO = 20A IO = 100A 1 / 2bias 1 / 3bias 1 / 3bias 1 / 3bias 1 / 3bias Low-power mode fOSC = 38kHz Pin CS, CK, DI, RES CS, CK, DI, RES CS, CK, DI, RES CS, CK, DI, RES S1 ~ S32 COM1 ~ COM3 S1 ~ S32 COM1 ~ COM3 COM1 ~ COM3 S1 ~ S32 COM1 ~ COM3 S1 ~ S32 COM1 ~ COM3 -- --
Output low level voltage
3
Standard ICs
BU9718KV
*AC characteristics (unless otherwise noted, Ta = 25C, VDD = 2.7V to 3.5V, VSS = 0V)
Parameter Guaranteed oscillation range Operating frequency Data set-up time Data hold time CS set-up time CS hold time CK "H" level pulse width CK "L" level pulse width Rise time Fall time Symbol fOSC fOSC tDS tDH tCS tCH tCKH tCKL tr tf Min. 10 -- 200 200 200 200 200 200 -- -- Typ. 38 -- -- -- -- -- -- -- -- -- Max. 80 100 -- -- -- -- -- -- 100 100 Unit kHz kHz ns ns ns ns ns ns ns ns Conditions C = 1000pF R = 47k External input -- -- -- -- -- -- -- -- Pin OSC OSC CK, DI CK, DI CS, CK CS, CK CK CK CS, CK, DI CS, CK, DI
AC timing waveform (1) When CK is stopped at "L"
0.8VDD CS tCS tCKH tCKL tCH 0.2VDD
0.8VDD 0.5VDD CK tDS tDH tr 0.5VDD
0.8VDD 0.2VDD tf
DI
Fig.1
(2) When CK is stopped at "H"
0.8VDD CS tCS tCKH tCKL tCH 0.2VDD
0.8VDD CK 0.2VDD tDS 0.5VDD tDH 0.5VDD tr tf 0.2VDD
DI
Fig.2
4
Standard ICs
Timing charts (1) When CK is stopped at "L"
CS
BU9718KV
CK D1 DI Display data Control code D2 D3 D95 0 0 0 0 0 BM LC OE
Fig.3
When CS is HIGH, data can be transferred. Data is sent to the shift register at the rising edge of CK. After all of the DI data has been transferred, CS should be set to LOW. The voltage corresponding to the display data transferred at the falling edge of CS is output. (2) When CK is stopped at "H"
CS
CK D1 DI Display data Control code D2 D3 D96 0 0 0 0 0 BM LC OE
Fig.4
Control code table
OE 0 1 Output enable control Normal operation No display; all display data = 0 (internal oscillation circuit is operating)
LC 0 1
Low-power mode control Normal operation Low-power mode = internal oscillation circuit has stopped; segment and common output = 0
BM 0 1
Bias mode control 1 / 3 bias 1 / 2 bias
5
Standard ICs
Correspondence between display data input and segments
Segment S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 S13 S14 S15 S16 COM3 D1 D4 D7 D10 D13 D16 D19 D22 D25 D28 D31 D34 D37 D40 D43 D46 COM2 D2 D5 D8 D11 D14 D17 D20 D23 D26 D29 D32 D35 D38 D41 D44 D47 COM1 D3 D6 D9 D12 D15 D18 D21 D24 D27 D30 D33 D36 D39 D42 D45 D48 Segment S17 S18 S19 S20 S21 S22 S23 S24 S25 S26 S27 S28 S29 S30 S31 S32 COM3 D49 D52 D55 D58 D61 D64 D67 D70 D73 D76 D79 D82 D85 D88 D91 D94 COM2 D50 D53 D56 D59 D62 D65 D68 D71 D74 D77 D80 D83 D86 D89 D92 D95
BU9718KV
COM1 D51 D54 D57 D60 D63 D66 D69 D72 D75 D78 D81 D84 D87 D90 D93 D96
6
Standard ICs
BU9718KV
*Output waveforms
fO = fOSC / 384 VDD COM1 VDD1, VDD2 VSS VDD COM2 VDD1, VDD2 VSS VDD COM3 VDD1, VDD2 VSS VDD LCD driver output, when all LCD segments for COM1, 2 and 3 are out VDD1, VDD2 VSS VDD LCD driver output, when only the LCD segment for COM1 is lit up VDD1, VDD2 VSS VDD LCD driver output, when only the LCD segment for COM2 is lit up VDD1, VDD2 VSS VDD LCD driver output, when the LCD segments for COM1 and 2 are lit up VDD1, VDD2 VSS VDD LCD driver output, when only the LCD segment for COM3 is lit up VDD1, VDD2 VSS VDD LCD driver output, when the LCD segments for COM1 and 3 are lit up VDD1, VDD2 VSS VDD LCD driver output, when the LCD segments for COM2 and 3 are lit up VDD1, VDD2 VSS VDD LCD driver output, when all the LCD segments for COM1, 2 and 3 are lit up VDD1, VDD2 VSS fO = fOSC / 384 VDD VDD1 VDD2 VSS VDD VDD1 VDD2 VSS VDD VDD1 VDD2 VSS VDD VDD1 VDD2 VSS VDD VDD1 VDD2 VSS VDD VDD1 VDD2 VSS VDD VDD1 VDD2 VSS VDD VDD1 VDD2 VSS VDD VDD1 VDD2 VSS VDD VDD1 VDD2 VSS VDD VDD1 VDD2 VSS
1 / 2 bias 1 / 3 duty waveform
1 / 3 bias 1 / 3 duty waveform
Fig.5
Fig.6
7
Standard ICs
BU9718KV
*Application example 1
47k 1000pF GND OSC
VDD
VDD RES
COM1 COM2 COM3
VSS S1 VDD1 VDD2 Controller BU9718KV S2 S3 S4 S5 C 0.047F CS CK DI S32 S6 96 Segment LCD
1 / 2 bias mode
Fig.7
47k 1000pF GND OSC
VDD
VDD RES
COM1 COM2 COM3
VSS S1 VDD1 VDD2 Controller BU9718KV S2 S3 S4 S5 C 0.047F CS CK DI S32 S6 96 Segment LCD
1 / 3 bias mode
Fig.8
8
Standard ICs
BU9718KV
*Application example 2
47k 1000pF GND OSC
VDD
VDD RES
COM1 COM2 COM3
VSS R S1 VDD1 VDD2 Controller R BU9718KV S2 S3 S4 S5 C 0.047F CS CK DI S32 S6 96 Segment LCD
1)
1 / 2 bias mode
Fig.9
47k 1000pF GND OSC
VDD
VDD RES
COM1 COM2 COM3
VSS
2)
R VDD1 R VDD2 BU9718KV
S1 S2 S3 S4 S5 96 Segment LCD
Controller R C 0.047F CS CK DI
S6
S32
1 / 3 bias mode
Fig.10
Note: The resistance values and capacitance for 1 and 2 should be set to match the LCD panel, and should be checked using test operation.
9
Standard ICs
BU9718KV
Make sure of the following when resetting when the power is on. * When using the external reset terminal, make RST = "L" at 1 ms or more with VDD at 2.7V or more. * When not using the external reset terminal,VDD has to satisfy the following conditions.
Instruction receipt possible VDD 2.7V tWAIT 1ms VDD < 0.3V 0 < tON < 10ms
*External dimensions (Units: mm)
9.0 0.3 7.0 0.2 36 9.0 0.3 7.0 0.2 37 48 1 1.425 0.1 0.10 25 24 13 12 0.5 0.125 0.1 0.10
0.5
0.2 0.1
VQFP48
10

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